1. Field of the Invention
The present invention relates to clock domain crossing. In one example, the present invention relates to methods and apparatus for efficiently selecting and implementing clock domain crossing adapters on a programmable chip system.
2. Description of Related Art
Primary and secondary components in an embedded system are typically associated with a particular clock domain. In one example, a hardware accelerator may be configured to operate at one particular clock rate, such as 500 MHz, while memory is configured to operate at another clock rate, such as 100 MHz. The hardware accelerator can be connected to other components having the same 500 MHz clock rate without requiring clock domain crossing mechanisms. However, clock domain crossing mechanisms are required to allow the hardware accelerator to interact with 100 MHz components such as memory in this example. Sending signals across clock boundaries can lead to data integrity problems if the signals are not properly synchronized.
One problem that can occur is metastability. Metastability occurs when the output of a register is in an unknown, fluctuating state. For example, clocking signals into a flip-flop without the proper setup times can cause metastability. Clock domain crossing logic and synchronizers are used to prevent metastability. Some of the more common mechanisms for clock crossing are two-stage synchronizers and four-way handshake mechanisms. Implementing clock domain crossing logic and synchronizers is an error-prone and inefficient process. Consequently, a variety of tools have been developed to aid in clock domain crossing verification and analysis.
In some examples, the complexity associated with clock domain crossing leads designers to implement systems entirely using a single clock domain. For example, a 100 MHz hardware accelerator can be configured to operate with 100 MHz memory. However, selecting only components based on a single, strict clock constraint can lead to suboptimal designs.
Techniques and mechanisms for implementing clock domain crossing mechanisms have significant limitations. Consequently, it is desirable to provide improved methods and apparatus for allowing efficient clock domain crossing management for programmable chip systems.